1. Field of the Invention
The present invention generally relates to semiconductor plating and other wet processing systems.
2. Description of the Related Art
Sub-quarter micron multilevel metallization is a key technology for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of these integration technologies generally possess high aspect ratio features, including contacts, vias, lines, plugs, and other features. Therefore, reliable formation of these features is critical to the success of VLSI and ULSI, as well as to the continued effort to increase integrated circuit density, quality, and reliability on individual substrates. As such, there is a substantial amount of ongoing effort being directed to improving the formation of void-free sub-quarter micron features having high aspect ratios, i.e., features having a height to width ratio of about 4:1 or greater.
Elemental aluminum (Al) and aluminum alloys have conventionally been used as conductive materials to form lines, plugs, and other features in integrated circuit semiconductor processing techniques, as a result of aluminum""s low resistivity, superior adhesion to silicon dioxide (SiO2) substrates, ease of patterning, desirable electromigration characteristics, and relatively high purity available at moderate costs. However, as circuit densities increase and the size of conductive features therein decreases, conductive materials having a lower resistivity than aluminum may be desirable. Therefore, copper and copper alloys are becoming choice metals for filling sub-quarter micron and smaller high aspect ratio interconnect features in integrated circuits, as copper and copper alloys have a lower resistivity than aluminum, and therefore, generate better resistance/capacitance time delay characteristics. Additionally, copper and copper alloys generally offer improved electromigration characteristics over aluminum.
However, a challenge with using copper in integrated circuit fabrication is that copper is not easily deposited into high aspect ratio features with conventional semiconductor processing techniques. For example, physical vapor deposition (PVD) techniques may be used to deposit copper, however, PVD copper deposition is known to encounter difficulty in obtaining adequate bottom fill in high aspect ratio features. Additionally, chemical vapor deposition (CVD) may be used to deposit copper, however, CVD suffers from relatively low deposition rates, and therefore low throughput, in addition to using precursors that are difficult to manage. Additionally, copper is difficult to pattern with conventional semiconductor processing techniques, and therefore, copper must generally be deposited directly into features, where conventional aluminum deposition techniques allowed for deposition and patterning of the conductive features. In view of these difficulties, electroless and electroplating deposition methods have become an attractive option for depositing metal, specifically copper, onto semiconductor substrates and into high aspect ratio features.
Electroless and electroplating methods generally include a substrate plating step followed by a substrate rinse and dry step. The plating step generally includes flowing a plating solution over the surface of the substrate in order to deposit a desired metal layer on the surface of the substrate. Once the desired metal layer is formed on the substrate surface, the substrate surface is generally rinsed and dried to remove any excess material or plating solution therefrom. The rinsing process generally includes flowing a rinsing fluid onto the surface of the substrate while the substrate is rotated on a support member. The rinsing fluid is urged radially outward by the rotation of the substrate, and therefore, the rinsing fluid operates to sweep away or rinse off any excess material or plating solution on the substrate surface. Once the rinsing process is complete, the substrate is generally rotated at a high rate of speed in order to remove any excess rinsing solution from the surface of the substrate. However, conventional spin rinse dry (SRD) apparatuses and methods generally do not provide fluid management capability, i.e., conventional apparatuses generally flow rinsing fluids across the surface of the substrate and then discard the fluid as waste. Further, conventional SRDs generally offer no control over the fluid dynamics as the fluid passes over the substrate surface.
Therefore, there exists a need for a method and apparatus for cleaning and/or rinsing substrates in a semiconductor processing system, wherein the method and apparatus includes the ability to control fluid dynamics and to minimize fluid waste.
Embodiments of the invention generally provide an apparatus and method for rinsing and drying a substrate. One embodiment of the invention provides a spin rinse dry chamber for a semiconductor processing system. The SRD chamber includes a processing enclosure having a selectively rotatable substrate support member positioned therein. The substrate support member includes an upper substrate receiving surface formed thereon. The SRD chamber further includes a selectively rotatable shield member positioned above the upper substrate receiving surface within the SRD chamber. The rotatable shield member generally includes a substantially planar lower surface that may be selectively positioned proximate the upper surface of the substrate.
Embodiments of the invention further provide a semiconductor processing apparatus having a substrate support member positioned within a processing enclosure, the substrate support member having an upper substrate receiving surface formed thereon. The processing enclosure further includes a disk shaped shield member positioned therein above the substrate receiving surface. The disk shaped shield member generally includes a substantially planar lower surface positioned in a substantially parallel orientation with the upper substrate receiving surface.
Embodiments of the invention further provide a method for rinsing semiconductor substrates, including the steps of positioning the substrate on a substrate support member, and positioning a shield member having a substantially planar lower surface in a processing position above the substrate such that the substantially planar lower surface is in parallel orientation with an upper surface of the substrate. The method further includes flowing a fluid solution into a minimized processing volume defined by the upper surface of the substrate and the substantially planar lower surface. The fluid may be communicated to the processing volume via a fluid aperture formed into the substantially planar lower surface.